Cyclic coding algorithms under MorphoSys reconfigurable computing system

The MorphoSys Parallel Reconfigurable System

This paper introduces MorphoSys, a parallel system-on-chip which combines a RISC processor with an array of coarse-grain reconfigurable cells. MorphoSys integrates the flexibility of general-purpose systems and high performance levels typical of application-specific systems. Simulation results presented here show significant performance enhancements for different classes of applications, as com...

The MorphoSys Dynamically Reconfigurable System-on-Chip

MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicat...

Design and Implementation of the MorphoSys Reconfigurable Computing Processor

In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architec...

2D and 3D Computer Graphics Algorithms under MORPHOSYS

This paper presents new mappings of 2D and 3D geometrical transformation on the MorphoSys (M1) reconfigurable computing (RC) prototype [2]. This improves the system performance as a graphics accelerator [1-5]. Three algorithms are mapped including two for calculating 2D transformations, and one for 3D transformations. The results presented indicate an improved performance. The speedup achieved ...

Reconfigurable Computing For Symmetric-Key Algorithms